1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a fuse circuit of a semiconductor apparatus.
2. Related Art
A semiconductor apparatus comprises various fuse options that can be used to repair defects occurred therein. Using one of the fuse options, a repair memory cell in a semiconductor apparatus such as a memory apparatus can replace a defective memory cell in the semiconductor apparatus in which data is stored.
Various types of fuses are used in fuse circuits, and the fuse circuits may be, for example, fuse options. One type of these fuses is an electrical fuse that may function as an anti-fuse. In general, the electrical fuse refers to a fuse which has high resistance to prevent current flow and is short-circuited when a voltage having a level equal to or higher than a predetermined level is applied to permit current flow. Hence, a fuse circuit comprising the electrical fuse can perform a fuse programming with application of a voltage having a level equal to or higher than the predetermined level, for example, a programming voltage.
FIG. 1 is a block diagram schematically illustrating the configuration of a typical fuse circuit. Referring to FIG. 1, the fuse circuit includes an address input buffer 10, a plurality of fuse sets FS1 through FSn, and a ring counter 20. The address input buffer 10 is configured to generate address signals ADD<1:n> which may represent information on whether to program the fuses provided in the fuse sets FS1 through FSn.
The plurality of fuse sets FS1 through FSn are configured to generate fuse signals FUSEOUT1 through FUSEOUTn in response to the address signals ADD<1:n>, a test mode signal TM, and fuse programming signals Q1 through Qn outputted from the ring counter 20. If some of the fuses are programmed, the corresponding fuse sets among the plurality of fuse sets FS1 through FSn invert the levels of the fuse signals FUSEOUT1 through FUSEOUTn using a programming voltage VPP.
The ring counter 20 is configured to receive a clock signal CLK and a reset signal RST, generate the fuse programming signals Q1 through Qn for actually performing fuse programming, and supply the fuse programming signals Q1 through Qn to the fuse sets FS1 through FSn. Accordingly, if the test mode signal TM is enabled in a test mode, the fuse circuit can program the fuses provided in the fuse sets FS1 through FSn in response to the fuse programming signals Q1 through Qn and the address signals ADD<1:n>.
FIG. 2 is a timing diagram illustrating the operations of the fuse circuit shown in FIG. 1. The operations of the typical fuse circuit will be described below with reference to FIGS. 1 and 2. When the test mode signal TM is enabled in the test mode and the reset signal RST is disabled, the ring counter 20 generates the fuse programming signals Q1 through Qn which are sequentially enabled. The ring counter 20 can comprise flip-flops which are connected in series, in which case it can generate the fuse programming signals Q1 through Qn which are sequentially enabled during their own predetermined intervals as shown in FIG. 2.
If the fuse programming signal Q1 is enabled, the fuse of the fuse set FS1 can be programmed using the programming voltage VPP, and if the fuse programming signal Q2 is enabled, the fuse of the fuse set FS2 can be programmed using the programming voltage VPP. If either of the fuses of the fuse sets FS1 and FS2 is programmed, the level of the corresponding fuse signal FUSEOUT1 or FUSEOUT2 is changed accordingly.
As described above with reference to FIGS. 1 and 2, the fuse programming of the plurality of fuse sets FS1 through FSn can be performed sequentially. However, as the fuse programming is continuously performed and the programming voltage VPP is frequently used, the level of the programming voltage VPP changes. Therefore, a problem of improper programming occurs when fuse programming is performed using a decreased programming voltage VPP by a certain level.